if(stall_count!=0) begin
  stall_count<=stall_count-1;
end
else if(w_enabler!=5'b11111) begin
  enabler<=w_enabler;
  stall_count<=3;
end

//FETCHER
if(w_enabler[1]==TRUE) begin
if_id_instr<=w_if_id_instr;
end


//WE get state from MEM
if(w_enabler[4]==TRUE) begin
we_wreg<=mem_wreg;
we_m2reg<=mem_m2reg;
we_reg_addr<=mem_reg_addr;
end
else begin
we_wreg<=FALSE; //which is not important for the next stage, thus can be canceled
end


//MEM
if(w_enabler[3]==TRUE) begin
//MEM get state from EX
mem_wreg<=ex_wreg;
mem_m2reg<=ex_m2reg;
mem_wmem<=ex_wmem;
mem_reg_addr<=ex_reg_addr;

//prepare data and address for MEM
mem_addr<=ex_b_val;
mem_in_val<=ex_out_val;
mem_out_val<=w_mem_out_val;
end
else begin
mem_wmem<=FALSE; //which is not important for the next stage, thus can be canceled
end


if(w_enabler[2]==TRUE) begin
//store data computed from the ALU into the EX/MEM register
ex_b_val<=w_ex_b_val;
ex_out_val<=w_ex_out_val;


//EX get state from ID(wire)
ex_reg_addr<=w_id_reg_addr; //for write
ex_reg_rs<=w_id_rs;
ex_reg_rt<=w_id_rt;
ex_wreg<=w_id_wreg;
ex_wmem<=w_id_wmem;
ex_m2reg<=w_id_m2reg;
ex_shift<=w_id_shift;
ex_aluc<=w_id_aluc;
ex_sa<=w_id_sa;
ex_signed_imm<=w_id_signed_imm;
ex_aluimm<=w_id_aluimm;

//store data fetched from the data register into the ID/EX register
out_a_val<=w_raw_a_val;
out_b_val<=w_raw_b_val;

id_jump<=w_id_jump;
id_j_addr<=w_id_j_addr;
end //else never move the data


//pass states, which means pipeline forward one cycle
//probe hazard
if(w_enabler[0]==TRUE) begin
pc<=(id_jump==TRUE)? {2'b00,{pc[word_size-1:word_size-4]},id_j_addr}:pc+1;
end
